BUILD SUPERMICRO X10SLM+-F and an i3-4330

[Fraoch]

(notably, the Devil's Canyon Haswell Pentiums don't support ECC).

Don't mean to call you out Eric :) but the only DC Pentium is the rather-special G3258:

http://www.anandtech.com/show/8079/...erclockable-pentium-i74790k-i54690k-and-g3258

and it does support ECC:

http://ark.intel.com/m/products/827...258-3M-Cache-3_20-GHz#@product/specifications

I believe some have reported it works fine in the Supermicro X10 motherboards, but you'd need the 2.0 BIOS for sure.

 

[Ericloewe]

Don't mean to call you out Eric :) but the only DC Pentium is the rather-special G3258:

http://www.anandtech.com/show/8079/...erclockable-pentium-i74790k-i54690k-and-g3258

and it does support ECC:

http://ark.intel.com/m/products/827...258-3M-Cache-3_20-GHz#@product/specifications

I believe some have reported it works fine in the Supermicro X10 motherboards, but you'd need the 2.0 BIOS for sure.

That's odd. It's definitely changed, since ark showed it as not supporting ECC back when it was announced. Thanks for the heads-up!

 

[DJABE]

Well, do you think it would be wise (read: silly expensive) for Intel to go and just disable ECC* support on that "anniversary" edition series of Haswell chip? Everything is the same like G3420, with one major difference - being unlocked.

____
* I'm not sure if it is possible to do it on EEPROM/Firmware/Bootcode level or it would require another memory controller built in...

 

[cyberjock]

Well, do you think it would be wise (read: silly expensive) for Intel to go and just disable ECC* support on that "anniversary" edition series of Haswell chip? Everything is the same like G3420, with one major difference - being unlocked.

____
* I'm not sure if it is possible to do it on EEPROM/Firmware/Bootcode level or it would require another memory controller built in...

Its already wicked easy for them to disable ECC. Pentiums are nothing but i3s with crap disabled, celerons are nothing but pentiums with crap disabled, etc. ;)

I bet it's trivially easy. Now whether they'd do it and add more confusion to the mix is another discussion entirely. BUT, I bet they could disable it with almost no effort whatsoever.

 

[Ericloewe]

Well, do you think it would be wise (read: silly expensive) for Intel to go and just disable ECC* support on that "anniversary" edition series of Haswell chip? Everything is the same like G3420, with one major difference - being unlocked.

____
* I'm not sure if it is possible to do it on EEPROM/Firmware/Bootcode level or it would require another memory controller built in...

I'm sure it's trivial (dunno if microcode or physical fusing, though): The Xeon E3s, i5s and i7s all share the same die (I guess Xeon-quality dies with crapped-out GPUs end up as the non-GPU Xeons).

I dunno how they match up exactly, but similarly, the Xeon E5-1650 v3 is the exact same thing as an i7-5930K, with ECC enabled (and possibly other features enabled as well).

 

[Ericloewe]

Ninja'd. That's what I get for getting sidetracked trying to identify all the major components on the die...

Another example: i5s and i7s (and low end/high end Xeon E3s) are the same thing, only the i7s (and equivalent Xeons) have Hyperthreading enabled.

 

[DJABE]

Yeah, old story from Core2Duo era (45nm chips). I still have excellent Celeron E3300, which is Core2Duo actually with 'crap disabled' = L2 cache which was not good for a Core2Duo, so instead of 3MB it has "only" 1 MB, but everything else is exactly the same as C2D big brother. They simply didn't wanted to waste the chip, and they simply re-branded it as "Celeron" with a very low price. Mine is working 24/7 @4.7 GHz, from original 2.5... :)
Same thing goes for AMD, I got Athlon 750K which is actually an full size APU with a bad GPU inside... price is much better thou :)

 

[Thinkcat]

Of course it does, why else would it have been recommended all this time?

Are you absolutely sure this time?

Now, in Ark, Ivy Bridge i3s do not support ECC, except for a few low power models, but Haswell i3s do.

I think that the only way to be sure about this is, and has always been, to own the CPU and then hope for cosmic rays. If there is a report on a fixed one bit error in the motherboard's logs, then the CPU has ECC. Otherwise one either needs a Xeon or plays Russian roulette with his data.

You must mean "every i3 after Ivy Bridge" instead of "since". But if this goes on as before, they will soon say "fool'd you" with i3 Haswells too. It is as if Intel was trying to prove a point that no consumer ever really needed ECC in the first place.

 

[Ericloewe]

Are you absolutely sure this time?

Now, in Ark, Ivy Bridge i3s do not support ECC, except for a few low power models, but Haswell i3s do.

I think that the only way to be sure about this is, and has always been, to own the CPU and then hope for cosmic rays. If there is a report on a fixed one bit error in the motherboard's logs, then the CPU has ECC. Otherwise one either needs a Xeon or plays Russian roulette with his data.

You must mean "every i3 after Ivy Bridge" instead of "since". But if this goes on as before, they will soon say "fool'd you" with i3 Haswells too. It is as if Intel was trying to prove a point that no consumer ever really needed ECC in the first place.

My comment above predated the last round of "Intel did what?". Going back to edit all posts is not a realistic option.

Currently, Ivy Bridge i3s apparently do not support ECC. All current indications are that Haswell i3s do support ECC - they report ECC is being used and Intel said they do after the Ivy Bridge incident. It's also theoretically possible to test them with ECC error injection, according to the datasheet, but I haven't seen any software that does so. It would probably have to run from a UEFI shell.

 

[DrKK]

My comment above predated the last round of "Intel did what?". Going back to edit all posts is not a realistic option.

Currently, Ivy Bridge i3s apparently do not support ECC. All current indications are that Haswell i3s do support ECC - they report ECC is being used and Intel said they do after the Ivy Bridge incident. It's also theoretically possible to test them with ECC error injection, according to the datasheet, but I haven't seen any software that does so. It would probably have to run from a UEFI shell.

So, here's the deal on this.

To the extent that people in the peanut gallery, like us, can inquire about these things, it has been done. We (meaning, members of the community that can be trusted) have spoken to actual Intel engineers who swear to Jesus, Buddha, and Allah, that the Haswell pentiums are good to go for ECC. So it is theoretically possible that they are all lying, but, as far as I can tell, they were quite embarrassed about the Ivy bridge SKUs being listed as supporting ECC when they did not, and I certainly believe they have double- and triple-checked the situation with the 1150 SKUs. I am comfortable saying that everything that can be done to verify that these support ECC has been done, and that all indications are strongly in the affirmative. AFAIAC, there is no serious FUD left on this one. Haswell Pentiums (pentia?) support ECC.

 

[DrKK]

Of course, Eric, if there is software to artificially inject an error, I'd welcome that. But short of that, we have the assurances we can have.

 

[Thinkcat]

https://queue.acm.org/detail.cfm?id=1839574

At least on the Sparc side it requires explicit hardware facilities to inject errors.

 

[Ericloewe]

Explicit hardware support is pretty much always necessary - but Haswell processors supposedly include this. The mystery is why nobody's written something that does this.

 

[DrKK]

Explicit hardware support is pretty much always necessary - but Haswell processors supposedly include this. The mystery is why nobody's written something that does this.

Well, maybe Sunday's uber-super-moon-lunar-eclipse will generate enough astrophysical disturbance to induce a variety of bitflips.

 

[cyberjock]

Explicit hardware support is pretty much always necessary - but Haswell processors supposedly include this. The mystery is why nobody's written something that does this.

Uhh, nobody has written something to do it because it is handled exclusively by the hardware. In Haswell it's supported because it's a new 'built-in' feature. What a "program" will do is tell the Haswell CPU or memory controller to inject an error. The program won't actually generate an error itself.

 

[Ericloewe]

Uhh, nobody has written something to do it because it is handled exclusively by the hardware. In Haswell it's supported because it's a new 'built-in' feature. What a "program" will do is tell the Haswell CPU or memory controller to inject an error. The program won't actually generate an error itself.

Of course, what I mean is that nobody has written the following pseudocode:

Code:

//init stuff

                                    MOV ECC_inject, R247
loop:                       BR loop

 

[Ericloewe]

If anyone's interested:
http://www.intel.com/content/dam/ww...datasheets/xeon-e3-1200v3-vol-2-datasheet.pdf

Page 257:
Register at offset 40b4h takes a 32-bit int that defines the number of chunks until the next ECC error injection. Default is 2^32-1, which is rather extreme.
Register at offset 40b8h takes one of 5 values, depending on the desired operation.

Page 259 has the equivalent registers for the second channel.

This should be enough to get a basic program going. Memory accesses (think memtest) are naturally still needed. IPMI log could be used to review test results.

I imagine this could be written to run in a UEFI shell...

 

[Ericloewe]

If anyone's interested:
http://www.intel.com/content/dam/ww...datasheets/xeon-e3-1200v3-vol-2-datasheet.pdf

Page 257:
Register at offset 40b4h takes a 32-bit int that defines the number of chunks until the next ECC error injection. Default is 2^32-1, which is rather extreme.
Register at offset 40b8h takes one of 5 values, depending on the desired operation.

Page 259 has the equivalent registers for the second channel.

This should be enough to get a basic program going. Memory accesses (think memtest) are naturally still needed. IPMI log could be used to review test results.

I imagine this could be written to run in a UEFI shell...

God, EFI is bloated. 46KB for a silly Hello, World! program? And system firmware is all like this? What a crazy world.

 

[morbloe]

How is this board regarding undervolting? I planning to use it with a xenon.

 

[jgreco]

How is this board regarding undervolting? I planning to use it with a xenon.

Typically the server grade boards don't support running CPU's outside of spec.