You were referring to the
Core i3-7100T CPU and I was puzzled by your answer because the datasheet says it does support ECC RAM. Did I get something wrong?
Oof, a post from nearly two years ago. I'd actually forgotten about that mess. As usual, blame Intel:
Initially, the i3-7xxx were a fairly delayed, fairly minor launch with lots of confusion, as Tick-Tock fell apart at that time. They're essentially the same parts as the 6xxx models, down to the die stepping. At first, ark.intel.com said they supported ECC. Then they changed it to no (and I think someone may have gotten a statement from Intel saying so). Then they changed it back a few months later.
What do I make of this? 7xxx models are probably fine, but they offer little to nothing over 6xxx models.
Is there any way to know which lanes are managed by the CPU and which lanes are managed by the chipset?
This is specified in the manual. For the X11SSM-F and similar boards, it's the two x8 slots. On boards with SAS3 onboard, it's the SAS controller and the x8 slot.
I would guess that the two x8 slots are wired to the CPU because the chipset seems to only support up to x4?
It would be a very stupid thing to do, as the PCH only has a x4 uplink to the CPU. They'd just be wasting lanes they could use for literally anything useful. If it's even possible, which I suspect isn't.