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- Feb 15, 2014
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Allow me to present a more readable version of what I think you're saying, for future readers who might struggle to understand, as I did, without full context:Hi...the LPC is a PCI-to-ISA connect regulator and is one of the two upheld BIOS boot areas; the C2000 can either boot from SPI (default) or LPC/ISA (set by means of outer sense pins at powerup). This is fixed in a venturing, and inquisitively the "fix" comprises of disposing of the capacity of muxing the LPC transport pins with GPIO - they as of now not become programming selectable. This is essentially ALL I've had the option to discover regarding the matter. There's a workaround which comprises of adding an outer 100 ohm resistor, yet it's not satisfactory what sticks this is added to. It's additional across two cushions on a connector on some Synology NAS units, so it's anything but a yield current limiter however in all likelihood a solid pullup or pulldown. This leads me to presume it truly goes on an arrangement sense pin. Intel hasn't made their "foundation level change" public. Following it out on a board is somewhat hard since the SoC is an enormous BGA bundle that would should be desoldered.
Does anybody find out about this? Like, for instance, where the resistor is added - specifically is it added to the LPC clock yields, or to the sense inputs?
C2000 can boot either from the LPC bus or from the SPI bus. This is selected [by applying a pull-up to the FLEX_CLK_SE0 / AH59 pin]. I suspect that the resistor fix is related to this.
My thoughts follow:
As it turns out, most systems do not boot from the LPC bus, but from SPI, which makes sense when you consider that SPI EEPROMs are everywhere, unlike LPC ROMs. In fact, the datasheet has this little gem:
LPC Clock: These signals are the clocks driven by the processor to the LPC devices.
Each clock can support up to two loads.
Note: If the primary boot device is connected via the LPC interface,
it should use LPC_CLKOUT[0]. Using the LPC interface for the boot
device is not supported at this time and may not ever be supported by
this Intel product. Only use the SPI interface for boot device connection.
My first thought was "oh crap, they're using the LPC clock pin to choose whether to boot from SPI or LPC" - but that's wrong. There are two LPC clocks and neither of them is shared with this pin. They are LPC_CLKOUT0 / AG51 and LPC_CLKOUT1 / AM49.
So why the hell do systems cease to boot? My only hypothesis is that Intel is doing something weird with these clocks internally that breaks if the LPC Clock isn't being driven correctly.
I also considered that the systems might be booting, but failing early in the system firmware code because they can't reach LPC devices - namely the BMC (ASRock C2x50D4I boards also use a SuperIO, which I think Supermicro does without). I think we can discard this because I have a system that boots but cannot communicate with the BMC on the LPC once I apply the resistor fix on the LPC clock.
It's also vaguely possible that the BMC might somehow be holding the host CPU in reset in the absence of an LPC clock. It's difficult to tell without schematics (which the motherboard vendors keep under lock and key), datasheets (which ASpeed keeps under lock and key) or a straight answer about the workaround (which Intel keeps under lock and key).
Edit: Might everyone be using FLEX_CLK_SE0 for the LPC clock instead of the LPC_CLKOUT pins? I think that's what ASRock is doing, their manual mentions that the SuperIO is communicating at 33 MHz, which is only supported by the Flex Clocks, not the LPC.
That doesn't explain Supermicro, which does run the LPC bus at 25 MHz. But maybe Intel's reference design used that pin and everyone just ran with it, because why would they waste engineering hours for no gain?
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